1. Field of the Invention
The present invention relates to forming a metal feature on an intermediate structure of a semiconductor device and, more specifically, to a method of selectively forming a metal feature on a first exposed metal structure of the intermediate structure without forming metal on a second exposed metal structure.
2. State of the Art
Fuses or fusible links are commonly used to connect electrical components on the surface of a semiconductor device with conductive traces to form circuit assemblies. Fuses are also used to provide a level of redundancy in the semiconductor device. For example, if a defective portion of the semiconductor device is found during testing or probe, the fuse connecting that portion is opened or blown, making that portion nonfunctional. However, since the semiconductor device is fabricated with many portions that perform the same function, the semiconductor device still functions after the fuse is opened. By building redundancies into semiconductor devices, manufacturers can increase their yields because devices that otherwise would be defective can still be used.
In intermediate structures of certain semiconductor devices, such as static random access memory (xe2x80x9cSRAMxe2x80x9d) and FLASH memory chips, fuses are exposed at the wafer level. The fuses are typically formed from conductive materials such as metals or polysilicon. The fuse is opened, or xe2x80x9cblown,xe2x80x9d by exposure to a laser beam or electrical current, which causes the metal or polysilicon to rapidly heat up and vaporize. This vaporized material is scattered and deposited across areas of the intermediate structure. In addition to causing shorts, the vaporized material may be undesirably deposited on the blown ends of the opened fuse, thereby reforming the two ends. The ends of the opened fuse may also be reformed if metal features are formed on the intermediate structure after the fuse has been opened. For example, metal of the metal feature may reform the fuse by spanning between the two, opened ends. Since the formation of metal features is necessary to electrically connect the semiconductor device, reformation of fuses opened during probe testing is problematic.
The aforementioned metal features may be formed by various techniques, depending on the desired semiconductor device. For example, the metal feature may be formed by chemical vapor deposition (xe2x80x9cCVDxe2x80x9d), physical vapor deposition (xe2x80x9cPVDxe2x80x9d), electroplating, or electroless plating. Electroless plating is used in the semiconductor industry to deposit thin, metal layers or features on the semiconductor device. Electroless plating is advantageous over other plating techniques because the plated metal is uniformly deposited and evenly coats all surfaces, including edges and corners. In contrast to electroplating, electroless plating does not utilize an electrical current to deposit the metal. However, electroless plating can only be used with particular metals because the metal must be catalytic in order to sustain the plating reaction. Metals that may be electrolessly plated include, but are not limited to, copper, nickel, palladium, tin, silver, and gold.
To electrolessly plate a metal feature on the intermediate structure, the intermediate structure is placed in an electroless plating solution that comprises metal ions, reducing agents, complexing agents, accelerators, and stabilizers. In the plating reaction, the metal ions are reduced to metal by oxidation of the reducing agent. The rate of deposition of the metal depends on the concentrations of the components of the electroless plating solution. For example, the concentration of stabilizer controls the plating reaction so that the metal is deposited at a predictable rate and on desired surfaces. The concentration of stabilizer also controls the rate of growth of the metal so that the metal is grown as a flat surface, rather than having dendritic growth. As disclosed in U.S. Pat. No. 6,335,626 to Motulla, the stabilizer concentration also affects the morphology of a contact metallization deposited on a terminal area.
Stabilizers used in electroless plating solutions include compounds of group VI elements, compounds containing oxygen, heavy metal cations, and unsaturated organic acids. Compounds comprising group VI elements that are used as stabilizers include, but are not limited to, sulfur, selenium, or tellurium compounds. Thiourea is a sulfur compound commonly used as a substrate. Compounds comprising oxygen that are used as stabilizers include, but are not limited to, AsO2xe2x88x92, IO3xe2x88x92, NO2xe2x88x92, BrO3xe2x88x92, or MoO4xe2x88x92. These anions may be used as potassium or sodium salts. Heavy metal cations including, but not limited to, Sn, Pb, Hg, or Sb are also used as stabilizers. Unsaturated organic acids including, but not limited to, maleic acid or itaconic acid are also used as stabilizers.
Many semiconductor manufacturers are starting to use copper in semiconductor devices, rather than aluminum. Copper wires are replacing aluminum wires because copper is more conductive and allows higher frequencies to be used with smaller linewidths. Copper is also replacing aluminum as the metal in bond pads. However, it is harder to create wirebonds to copper. With aluminum, ultrasonic vibrations are used to create an effective bond by breaking through aluminum oxide that forms on an aluminum bond pad""s surface. However, copper oxide is less brittle than aluminum oxide and, therefore, ultrasonic vibrations do not break through the copper oxide that forms on a copper bond pad""s surface. Rather, the copper oxide is ductile, with weak adherence to the metal""s surface, and the vibrations cause the wires to slide on the bond pad surface.
One method of wirebonding to copper comprises first forming a thin layer of another metal over the copper. The metal layer, which comprises aluminum, palladium, nickel, or gold, forms a cap structure over the copper. These metals are typically electrolessly plated or immersion plated onto the copper. The copper may also be capped or coated with multiple layers of metals, such as an interconnect cap. For example, the copper is capped with a thin layer of palladium, a thin layer of nickel, and a thin layer of gold, in ascending order. However, one disadvantage associated with these plating steps is that the metals used in the interconnect cap are also plated onto other metal portions of the semiconductor device. For example, if a fuse on the semiconductor device has been opened, the metals used in the interconnect cap plate on and between the ends of the opened fuses, thereby reforming the fuse.
In light of the problems discussed above, it would be advantageous to form a metal feature on a semiconductor device without the metal of the metal feature forming on other portions of the semiconductor device. Specifically, it would be advantageous to electrolessly plate a metal feature onto the semiconductor device without the metal of the metal feature plating other portions of the semiconductor device.
The present invention relates to a method of forming a metal feature on an intermediate structure of a semiconductor device that comprises a first exposed metal structure and a second exposed metal structure. By adjusting a concentration of stabilizer in an electroless plating solution, the metal feature may be formed on the first exposed metal structure without any metal of the metal feature being formed on the second exposed metal structure.
In a more specific implementation, the method includes selectively forming a metal feature on an intermediate structure of a semiconductor device that has been probed or otherwise tested. The method comprises providing the intermediate structure having a first exposed metal structure and a second exposed metal structure. The metal feature is electrolessly plated on the first exposed metal structure by adjusting a concentration of stabilizer in an electroless plating solution. The metal feature may comprise a metal layer, an interconnect cap, a redistribution layer, or a bond pad.
The stabilizer may be selected from compounds of group VI elements, compounds comprising oxygen, heavy metal cations, or unsaturated organic acids. The concentration of stabilizer may be either increased or decreased to selectively plate the metal feature. If the stabilizer concentration is increased, a critical size of the first exposed metal structure is decreased and a size of the metal feature is decreased. If the stabilizer concentration is decreased, the critical size of the first exposed metal structure is increased and a size of the metal feature is increased.
The intermediate structure may be an intermediate structure of an SRAM or FLASH memory chip that comprises at least one bond pad and at least one opened fuse. The metal feature is electrolessly plated onto the at least one bond pad, without reforming the opened fuse, by adjusting the concentration of stabilizer.
The present invention also comprises a method of optimizing an electroless plating solution to selectively plate a metal feature on a first exposed metal structure of an intermediate structure. The method comprises providing the electroless plating solution comprising a stabilizer. The concentration of stabilizer is adjusted to electrolessly plate the metal feature on the first exposed metal structure without depositing the metal of the metal feature on a second exposed metal structure. The first exposed metal structure and the second exposed metal structure may be viewed by scanning electron microscopy (xe2x80x9cSEMxe2x80x9d) to determine whether the metal feature is selectively plated on the first exposed metal structure.
The present invention also includes an intermediate structure of a semiconductor device. The intermediate structure comprises at least one opened fuse and a metal feature that has been electrolessly plated on a first exposed metal structure of the intermediate structure. Specifically, the first exposed metal structure comprises a copper bond pad that has been electrolessly plated with a nickel layer without reforming the at least one opened fuse.